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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33397/D Rev 2.0, 03/2003
Advance Information Dual/Hex Low-Side Switch with Both SPI and Parallel Input Control
The 33397 is a low-side switch that is user configurable to be either two 333 m outputs (dual mode) or six 900 m outputs (hex mode). Each output is internally current limited and short-circuit protected. Output fault detection capability includes "off state" open loads and "on state" short-to-battery conditions. Faults for each output are latched into the fault register and serially shifted out during serial communication.
33397
DUAL/HEX LOW-SIDE SWITCH
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Features * User Configurable to be Either Two 333 m Outputs (Dual Mode) or Six 900 m Outputs (Hex Mode) * Output Inductive Energy Clamps * Parallel Input (3.3 V and 5.0 V Compatible) or Serial Peripheral Interface (SPI) Control * 8-Bit SPI Control and Fault Diagnostics * Short-to-Battery Detection and Shutdown with Automatic Retry * OFF-State Open-Circuit Detection * Programmable Overvoltage Shutdown (VPWR Pin) * Undervoltage Shutdown (VDD Pin) * Sleep Mode--IDD 25 A (1.0 A Typical)
DW SUFFIX PLASTIC PACKAGE CASE 751E 24-LEAD SOICW
ORDERING INFORMATION
Device MC33397DW/R2 Temperature Range (TA) -40 to 125C Package 24 SOICW
33397 Simplified Application Diagram
EN VDD 13
33397
VPWR 24 A0 23 A1 14
+VBAT
Microcontroller with Bus
EN 15 CS 10 SCLK 3 SI 4
CMOS Input Logic
CMOS Serial Shift Registers and Latches
Output Switches and Sense Circuits
A2 12 A3 11 A4 2
SO 9
A5 1
GND 5-8, 17-20
This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc. 2003
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CS SI
SO SCLK
A0
3.0 V + Sleep Mode 50 V 1.2 ILIMIT Dual Mode 40 A Logic
8-Bit SPI Interface
+ - 3.0 V Sleep Mode 40 A Logic ILIMIT Dual Mode + 3.0 V Sleep Mode 40 A 50 V 1.2 ILIMIT 50 V 1.2
A1
A4
3.0 V + Sleep Mode 50 V 1.2 ILIMIT 40 A Logic Dual Mode 3.0 V + Sleep Mode 50 V 1.2 ILIMIT 40 A Logic Logic Logic
A2
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Dual Mode + - 3.0 V A3 Sleep Mode 40 A 50 V 1.2 ILIMIT
A5
P0 10 A
Parallel Gate Control and Mode Control Logic 10 s Filter Overvoltage Shutdown Low VDD Detect and POR Timer
P1 10 A 30 V + 3.0 V VDD VPWR
P2 10 A
+ 0.75 VDD 0.25 VDD + -
SQ R
VDD
EN
Figure 1. 33397 Simplified Block Diagram
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A5 A4 SCLK SI GND GND GND GND SO CS A3 A2
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VPWR A0 P2 P1 GND GND GND GND P0 EN A1 VDD
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PIN FUNCTION DESCRIPTION
Pin 1, 2, 11, 12, 14, 23 3 4 5-8, 17-20 9 10 13 15 16 21 22 Pin Name A0-A5 SCLK SI GND SO CS VDD EN P0 P1 P2 Power outputs SPI clock input SPI serial input Power and signal ground SPI serial output SPI chip select Supply input pin Enable In hex mode, P0 controls output A0. In dual mode, P0 controls outputs A0, A4, and A5 simultaneously In hex mode, P1 controls output A1. In dual mode, P2 controls outputs A1, A2, and A3 simultaneously In hex mode, P2 controls output A2. P2 is also the mode control pin. If 0.25*VDD24
VPWR
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MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted.
Rating Power Supply Voltage Logic Supply Voltage Input Pin Voltage ESD Voltage Human Body Model (Note 1) Machine Model (Note 2) Single Pulse Output Clamp Energy VESD1 VESD2 JCLAMP1 JCLAMP1 fOP TSTG TJ TSOLDER RJ-L 2000 200 mJ 50 100 3.5 -55 to 150 -40 to 150 260 15 MHz C C C C/W Symbol VPWR VDD VIN Value 50 -0.3 to 7.0 -0.3 to VDD+0.3 Unit V V V V
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IO =500 mA, TJ =150C (Hex Mode) IO =1.5 A, TJ =150C (Dual Mode) Recommended SPI Operating Frequency Storage Temperature Operating Junction Temperature Soldering Temperature (for 10 Seconds) Thermal Resistance, Junction-to-Lead (Note 3)
Notes 1. ESD1 performed in accordance with the Human Body Model (CZAP =100 pF, RZAP =1500 ). 2. 3. ESD2 performed in accordance with the Machine Model (CZAP =200 pF, RZAP =0 ). Leads 5, 6, 7, 8, 17, 18, 19, and 20 are soldered to a heat-sinking ground plane. See Figure 14.
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STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75 V VDD 5.25 V, -40C TA 125C, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER INPUT
VPWR Supply Current (All Outputs ON) VPWR Sleep State Supply Current VPWR =17 V, SPI Bit 7=1, EN=5.0 V Overvoltage Shutdown Overvoltage Shutdown Hysteresis IPWR(ON) IPWR(SS) VP(OV) VP(OV)Hys IDD IDDSS VDD(LVI) - 1.0 50 A A - 30 0.3 - - 2.5 1.0 33 0.5 1.20 1.0 3.0 10 38 1.5 5.0 25 3.5 V V mA A V
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Logic Supply Current (All Outputs ON) Logic Supply Current (Sleep State: EN=5.0 V, SPI Bit 7=1) Logic Supply Undervoltage Inhibit Threshold
INPUT
Input Voltage (P0, P1, P2, EN, SI, SCLK, CS) High Low Dual Mode Threshold (P2) Upper Threshold Lower Threshold Input Current Pull-Down (P0, P1)-VIN =VDD Pull-Down (P2)-VIN =VDD Pull-Up (CS)-VIN =0 V Pull-Up (EN)-VIN =0 V Pull-Up (SCLK, SI)-VIN =2.5 V IINPD IINPD IINPU IINPU IINPU 10 5.0 -20 -100 -10 20 10 -10 - 0 30 30 -5.0 -10 10 VDMH VDML 0.7 0.2 0.75 0.25 0.8 0.3 A VIH VIL 0.8 - - - - 0.2 VDD VDD
OUTPUT
Output Drain to Source ON Resistance (Hex Mode) (Note 4) IO =0.35 A, TJ =-40C IO =0.35 A, TJ =25C IO =0.35 A, TJ =150C Output Voltage Clamp IDS =20 mA, Output Off IDS =200 mA, Output Off Output Leakage Current (Hex Mode) EN=H, bit 7=1, VDRAIN =24 V Output Logic Voltage (SO), ILOAD =1.0 mA High Low Output Tristate Leakage (SO), VSO =2.5 V VOH VOL ISOT IO(SS) BVDSS RDS(ON) 0.39 0.51 0.51 0.5 0.7 1.0 1.2 1.2 1.2 V 50 50 55 56 60 60 A 0 - 10 VDD
0.8 - -10
- - -
- 0.2 10
A
Notes 4. This parameter is specified for hex mode. In dual mode, the parameter will be three times smaller.
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STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V VDD 5.25 V, -40C TA 125C, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
FAULT DETECTION
Output Self-Limiting Current (Hex Mode) (Note 5) Outputs Programmed ON Output Fault Detect Threshold Voltage Outputs Programmed OFF, EN=0 Output OFF Open Load Detect Current Output Programmed OFF, EN=0 Notes 5. This parameter is specified for hex mode. In dual mode, the parameter will be three times smaller. IO(OFF) 20 40 80 VOF(TH) 0.5 0.6 0.7 A IO(LIM) 1.0 1.5 2.0 VDD A
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DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75 V VDD 5.25 V, -40C TA 125C, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
OUTPUT TIMING
Output Rise Time VPWR =14 V, RLOAD =25 , 20-80% Output Fall Time VPWR =14 V, RLOAD =25 , 80-20% Output Turn-On Propagation Delay Output Turn-Off Propagation Delay tPON tPOFF tF 1.0 1.0 1.0 2.0 4.0 4.0 10 10 10 s s tR 1.0 1.2 10 s s
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FAULT TIMING
Output Short-to-Battery Fault Filter Time Output Refresh Timer Output Refresh Timer Duty Cycle Output Off-State Open Circuit Fault Filter Time tSS tREF D tOOF 30 3.0 0.2 30 50 4.1 1.56 50 90 6.0 3.0 90 s ms % s
SPI/MISCELLANEOUS TIMING
SO Disable Time (10 K Pull-Up Resistor on SO) CS=0.8 V to SO > 0.8*VDD SO Enable Time (10 K Pull-Up Resistor on SO) CS=0.8 V to SO Low Impedance SO Rise Time CL < 200 pF SO Fall Time CL < 200 pF SO Valid Time Falling Edge of SCLK to SO Valid Required Time Between Falling Edge of CS to Rising Edge of SCLK Required TIme Between Rising Edge of CS to Falling Edge of SCLK Required Time Between SI to Rising Edge of SCLK POR/EN Wake-Up Timer Mode Change Timer (P2) tLEAD tLAG tSU tPOR tMODE tVALID - - - - 20 5.0 65 100 0 25 40 10 80 ns 140 ns 50 45 60 25 ns s s tSOFALL - 30 50 ns tSORISE - 30 50 ns tSOEN - 80 110 ns tSODIS - 80 110 ns ns
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Timing Diagrams
CS
tLEAD
tLAG
SCLK
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SI
tSU
SO
tSOEN
tVALID
tSODIS
Figure 2. SPI Timing Diagram
CS
SCLK SI HIZ SO PO P1 P2 EN A0
tPON tFALL tRISE
A1
A2
tPOFF
A3-A5 Note: In hex mode, the outputs are controlled by the SPI or by the parallel inputs. However, P0, P1, and P2 only control A0, A1, and A2, respectively. When EN goes high, the part is disabled.
Figure 3. Operation Waveforms for Hex Control
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VDD 0.8 VDD P0, P1 0V tPON tR tPOFF 0.2 VDD
tF 80%
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VDS 0V
20%
Figure 4. Response Times
Short-to-Battery Period VDD
VIN (P0, P1)
VDS
ILIMIT ILOAD ILOAD
tREF tSS
tREF
Figure 5. Short-to-Battery Fault
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VDDLV1 VDD tPOR
Power On Reset (Internal Signal)
2.5 V P2 tMODE
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Hex Mode A2
tMODE
Dual Mode
Figure 6. Power On Reset and Mode Select
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TYPICAL CHARACTERISTICS
1.2 1 CURRENT (A) -25 0 25 50 75 100 125 150 0.8 RDS(ON) () 0.6 0.4 0.2 0 -50 0.2 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 -50 -25 0 25 50 75 100 125 150
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TA, AMBIENT TEMPERATURE (DEG C)
TA, AMBIENT TEMPERATURE (DEG C)
Figure 7. Output on Resistance versus Temperature
Figure 10. IVPWR versus Temperature
1.4 1.3 5V SUPPLY CURRENT (A) 1.2 1.1 1 0.9 0.8 -50
58 57.8 DRAIN TO CLAMP (V) 57.6 57.4 57.2 57 56.8 56.6 56.4 56.2 -50 -25 0 25 50 75 100 125 150
-25
0
25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (DEG C)
TA, AMBIENT TEMPERATURE (DEG C)
Figure 8. Drain to Source Clamp versus Temperature
1.74 1.72 2.5 1.7 CURRENT (A) CURRENT (A) 1.68 1.66 1.64 1.62 1.6 1.58 -50 -25 0 25 50 75 100 125 150 0.5 0 -50 2 1.5 1
Figure 11. IDD versus Temperature
3
-25
0
25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (DEG C)
TA, AMBIENT TEMPERATURE (DEG C)
Figure 9. Current Limit versus Temperature
Figure 12. IDD Sleep State versus Temperature
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SPI Input Word Definition
MSB 7 6 5 4 3 2 1 0
SPI Output Word Definition
MSB 7 6 5 4 3 2 1 0
<-DIN A0 Enable A1 Enable A2 Enable A3 Enable A4 Enable A5 Enable Not Used (Don't Care) Enable Sleep Mode
<-DIN A0 Fault A1 Fault A2 Fault A3 Fault A4 Fault A5 Fault Zero Sleep Mode Feedback (1=Sleep Mode Enabled)
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The device will power up with sleep mode enabled. In dual mode, input bits 0, 4, and 5 must all be high to turn on combinational output A0, A4, and A5 via the SPI. In dual mode, input bits 1, 2, and 3 must all be high to turn on combinational output A1, A2, and A3 via the SPI.
Figure 13. SPI Input/Output Word Definition Table 1. Truth Table
Inputs P0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 X P1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 X P2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V X EN 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 SPI Bit7 X X X X X X X X 0 0 0 0 0 0 0 0 X X X X 0 0 0 0 1 Outputs A0 OFF OFF OFF OFF ON ON ON ON OFF OFF OFF OFF ON ON ON ON OFF OFF ON ON OFF OFF ON ON OFF A1 OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF ON OFF ON OFF ON OFF ON OFF A2 OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF A3 * * * * * * * * OFF OFF OFF OFF OFF OFF OFF OFF OFF ON OFF ON OFF ON OFF ON OFF A4 * * * * * * * * OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON OFF OFF ON ON OFF A5 * * * * * * * * OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON OFF OFF ON ON OFF All outputs disabled. SPI is reset and ignored. No fault detection. DUAL MODE Outputs are not controlled via SPI. Outputs are controlled via inputs P0 and P1. Sleep mode disabled. DUAL MODE Outputs are also controlled via SPI. SPI fully functional. HEX MODE Outputs A3, A4, and A5 are always OFF. Outputs are not controlled via SPI. Outputs A0, A1, and A2 are only controlled via inputs P0, P1, and P2. Sleep mode disabled. HEX MODE * = Outputs A3, A4, and A5 are SPI controlled only. X = Don't care. Outputs A0, A1, and A2 are controlled either via SPI or inputs P0, P1, and P2. Comments
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65
60
55
PCB Heat Sink Flag 1
PCB Heat Sink Flag 2
C/W
50
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45 0 1 2 3 4 5 6 7 8 Total Square Inches of Heat Sink Flag Area (Flag 1 + Flag 2) 9 10
Figure 14. Approximate Thermal Resistance Using PCB Heat Sinking
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33397 is a versatile dual-mode low-side switch that can be output-configured as two 333 m open drain outputs in the dual mode or as six 900 m open drain outputs in the hex mode (RDS(ON) @ 25C). Each open drain output has internal current limit and shortcircuit protection. Current limit is typically 1.5 A, with 2.0 A maximum. The outputs can be input controlled via parallel inputs or the SPI. Three inputs provide parallel control, while a serial 8-bit word provides SPI control of the outputs. Output fault detection capability includes OFF-state open loads and ONstate short-to-battery conditions. Individual output faults are latched into the fault register and serially shifted out during serial communication to the 33397. The 33397 has both overvoltage and undervoltage shutdown. A low quiescent current sleep slate feature can be enabled or disabled on command via the SPI port.
FUNCTIONAL PIN DESCRIPTION
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VDD
Logic power supply pin.
In hex mode, P2 is the parallel input to control output A2. It is OR'd with SPI bit 2 to enable output A2. Either one will enable output A2. P2 also is used to program the 33397 to either a dual or hex output device. The 33397 will be the hex mode if P2 is biased above 0.75*VDD (typical) or below 0.25*VDD (typical). Normal 5.0 V control logic on this parallel input will maintain the 33397 in hex mode and allow control of output A2. If 0.25*VDD A0-A5
A0-A5 are the drains of the 1.2 (max.) MOSFETs. They each have an internal voltage clamp of 50 V (min.) to clamp inductive loads during turn-off. When enabled, they are each internally current limited to a maximum of 2.0 A. If any output is in current limit (output voltage >3.0 V) for a time greater than tSS, the output will be disabled for a time tREF and then try to turn on again. When disabled, open circuits are detected if the output is less than 3.0 V for a time of tSS. Either type of fault is reported as a fault on the SPI output word. If EN input is high and SPI bit 7=1, the pull-down current sources on the outputs are disabled to minimize VDD supply current. In hex mode, all six outputs are independent. Outputs A0, A1, and A2 are controlled by either the SPI input word bits 0, 1, and 2, respectively, or parallel inputs P0, P1, and P2. Outputs A3, A4, and A5 are controlled only by SPI input word bits 3, 4, and 5, respectively. In dual mode, outputs A0, A4, and A5 are all controlled simultaneously by input P0 or by SPI bits 0, 4, and 5. All three bits must be high to enable this output via the SPI. Outputs A1, A2, and A3 are all controlled simultaneously by input P1 or by SPI bits 1, 2, and 3. All three bits must be high to enable this output via the SPI.
VPWR
VPWR is used to sense an overvoltage condition on the supply pin. When the voltage on VPWR exceeds VOV, all outputs are disabled for the duration of the overvoltage condition. If VPWR is grounded, overvoltage shutdown is disabled. VPWR threshold can be modified with an external resistor divider if higher thresholds are desired.
SCLK
SCLK is the clock for the serial interface.
SI
SI is the serial input for the SPI port. When CS is low, SI is read on the positive edge of SCLK and SO is updated on the falling edge. When CS is high, SI is ignored. SI has a pull-down current source to pull it low in the event of an open circuit.
P0-P2
In hex mode, P0 is the parallel input to control output A0. It is OR'd with SPI bit 0 to enable output A0. Either one will enable output A0. In dual mode, P0 controls outputs A0, A4, and A5 simultaneously. P0 has a pull down current of 10 A. It is ignored when EN is high and bit 7=1. In hex mode, P1 is the parallel input to control output A1. It is OR'd with SPI bit 1 to enable output A1. Either one will enable output A1. In dual mode, P1 controls outputs A1, A2, and A3 simultaneously. P1 has a pull-down current of 10 A. It is ignored when EN is high and bit 7=1.
SO
SO is the serial output of the SPI port. When CS goes low, SO outputs bit 7 of the output word. On each falling edge of SCLK, SO will shift the next SPI output bit until on the eighth SCLK falling edge the bit present on SI during the first rising edge will appear. In this way devices can be daisy-chained to operate on a common CS. When CS is high, SO is high impedance.
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CS
CS is the chip select to enable the SPI interface. When CS is high, no SPI communication is possible. When CS goes low, SI will be read on each rising SCLK edge and SO will shift on each SCLK falling edge. When CS goes high, the bits present in the SPI input register will be interpreted as the SPI input command. Also when CS goes high, all faults that were latched into the SPI output register are cleared. If faults are still present on outputs, they will be re-latched after tSS.
or when the IC is powered up from VDD, a power-up timer of 40 s is started to allow the 33397 to determine which mode it is in (hex or dual). During this time all parallel inputs and serial control SPI bits will be ignored and all outputs will remain off. If EN transitions low when not in the sleep mode, this "dead" time will not occur. If a one was written to bit 7, the 33397 will be in the sleep mode when EN goes high. In this mode all SPI registers are reset to zero and all faults are cleared. No fault detection is possible. The standby supply current on VDD and VPWR is minimized.
EN
EN must be low for complete IC functionality in either the dual or hex mode. When EN transitions low while in the sleep mode
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APPLICATIONS
A voltage on the P2 input pin determines the mode. All six outputs can operate either independently (hex mode) (Figure 15) or in paralleled groups of three (dual mode) (Figure 16). In the dual mode, outputs A0, A1, and A2 are controlled by parallel inputs P0, P1, and P2, respectively, and they are also controlled by the SPI port with which they are OR'd. On the other hand, outputs A3, A4, and A5 are controlled only through the SPI port. When the voltage on P2 is between 0.25 VDD and 0.75 VDD (i.e., when P2 is held at an intermediate voltage, neither high nor low), the 33397 operates in the dual mode. However, the P2 pin must stay at that level for a minimum specified time. In this mode, outputs A0, A4, and A5 are all controlled in parallel by input P0. Outputs A1, A2, and A3 are all controlled in parallel by input P1. Both outputs can also be controlled via the SPI port as well, but only if the three outputs are commanded ON at the same time.
VBAT
VBAT VBAT
VBAT
VBAT
33397
A5 A4 SCLK SI GND VPWR A0 P2 P1 GND GND GND GND P0 EN A1 VDD VDD A5 A4 SCLK SI GND
33397
VPWR A0 P2 P1 GND GND GND GND P0 EN A1 VDD
VBAT VDD
To Microprocessor
GND GND GND SO CS
Parallel Inputs (Optional)
To Microprocessor
VBAT
GND GND GND SO
Parallel Inputs (Optional)
From Microprocessor
VBAT
CS A3 A2
From Microprocessor
VDD
VBAT VBAT
A3 A2
Figure 15. Hex Mode Application Circuit
Figure 16. Dual Mode Application Circuit
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PACKAGE DIMENSIONS
DW SUFFIX (24-LEAD SOIC WIDE BODY) PLASTIC PACKAGE CASE 751E-04 ISSUE E -A24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0x 8x 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0x 8x 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
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1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -TSEATING PLANE X 45
M
22X
G
K
DIM A B C D F G J K M P R
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NOTES
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NOTES
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NOTES
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Freescale Semiconductor, Inc...
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MC33397/D

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